Do graphic cards have instruction sets of their own?

Question

Do graphic cards have instruction sets of their own? I assume they do, but I have been wondering if they are proprietary or if there is some sort of open standard.

Is every GPU instruction preceded by a CPU instruction or is it seamless?

That is, does OpenGL or DirectX call on the driver layer via the CPU which then sends a GPU instruction down the bus or is it more elaborate?

Answer 1

Yes they do. AMD even provides the specification up to the HD4000 series at the moment.

Take a look here at AMD's R700 instruction set reference guide.

There is also an open source project called Nouveau that does reverse engineering of the Nvidia instruction sets.

Note that Nvidia has a slightly different architecture than AMD because they do not use VLIW but scalar execution (although multiple threads are additionally grouped in what is called a Warp or a Wavefront).

Also, not every OpenGL/Direct3D call maps to a "GPU instruction". For example, when binding a texture the driver will only set appropriate hardware registers that tell the GPU which texture memory to use for sampling.

Real programs are only run when executing shaders or stream processing kernels on the GPU.

Answer 2

Yes, the GPU have their own proprietrary instruction sets. The GPU instructions are executed independent from the CPU instructions.

Answer 3

Currently, NVIDIA cards use some kind of intermediate ISA called PTX. You can read about it in this document:

PTX ISA 1.1

PTX programs are translated at install time to the target hardware instruction set.

Answer 4

For nvidia cards you might want to have a look at this document http://docs.nvidia.com/cuda/cuda-binary-utilities/index.html#instruction-set-ref

Answer 5

AMD Graphics Core Next (GCN)

https://en.wikipedia.org/wiki/Graphics_Core_Next

The first generation is called "Southern Islands".

The wiki page links to AMD specs that document the ISA, e.g.: http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf

There is even an open RTL implementation called MIAOW https://github.com/VerticalResearchGroup/miaow, although it likely infringes some IP which AMD has merely chosen to tolerated in silence for now (source).

SPIR-V

https://en.wikipedia.org/wiki/Standard_Portable_Intermediate_Representation is a Krhonos standard intermediate language.

It is likely designed to be similar to existing GPU ISAs, so that it will be more implementable and have better adoption, so it should give a good idea of actual GPU ISAs.

And if this standard does catch on, as it seem to be the case due to adoption in Vulkan and OpenCL 2.1, future implementations are likely be designed to implement is closely to have better performance.

How to obtain and modify PTX

How to create or manipulate GPU assembler?

Related

https://computergraphics.stackexchange.com/questions/7809/what-does-gpu-assembly-look-like

Answer 6

See: CUDA Programming Guide Version 3.0

The compute capability of a device is defined by a major revision number and a minor revision number.

Devices with the same major revision number are of the same core architecture. The major revision number of devices based on the Fermi architecture is 2. Prior devices are all of compute capability 1.x (Their major revision number is 1).

The minor revision number corresponds to an incremental improvement to the core architecture, possibly including new features.

Appendix A lists of all CUDA-enabled devices along with their compute capability. Appendix G gives the technical specifications of each compute capability.