1
votes

My scenario is as follow:

  • One board acted as the PCIE Rootport (RP) and one board acted as PCIE Endpoint (EP).
  • The PCIE Endpoint exported a memory region. This memory region is shared between the RP and EP. Whenever we need to access this shared memory region (actually we just access the first few byte control data structure in this region). We have to do a invalidate cache for reading and flush cache after writing.
  • I tried to declare the structure as below, but without the invalidate/flush cache, the read/write does not take effect.

    typedef volatile struct { u32 front; u32 rear; u32 n_msg; u32 offset; } queue_ctl_t;

May anyone please tell me the correct way to access this shared memory region. I just wonder how some network drivers (for network cards on PCIE bus) can access the data consistently without doing the invalidate/flush cache. Any suggestions are appreciated, thank a lot!

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1 Answers

1
votes

You should be using ioremap_nocache() to map the memory regions in question, and reading/writing them using the ioread*() and iowrite*() functions.