I have a basic linux device driver module :
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
static int __init hello_init(void)
{
printk(KERN_ALERT "Hello, world \n");
return 0;
}
static void __exit hello_exit(void)
{
printk(KERN_ALERT "Goodbye, world \n");
}
module_init(hello_init);
module_exit(hello_exit);
I am able to compile this module in traditional way which is by using a simple Makefile which uses obj-m , but I want to compile this using command line gcc. This is because I can use gcc -save-temps flag to see the intermediate generated files(this can be particularly helpful to understand as Linux kernel uses lot of preprocessor stuff).
So is there a way to compile using command line gcc ??
EDIT Attaching the Makefile I have used
ifeq ($(KERNELRELEASE),)
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
EXTRA_CFLAGS+= -save-temps
modules:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
modules_install:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules_install
clean:
rm -rf *.o *~ core .depend .*.cmd *.ko *.mod.c .tmp_versions
.PHONY: modules modules_install clean
else
obj-m := hello.o
endif
gccfrom the command line successfully depends on setting up the shell environment properly. That is (partly) whatmakeandMakefileare for. If you really insist on using the shell, then you should append yourMakefileto your question for review. - sawdust