Serial Peripheral Interface

1
votes

I was going through an article related to SPI. There was a configuration named 'Daisy Chaining', in case of multiple slaves.

So far, what I have understood about SPI (based on wikipedia) is,

SPI can transfer and receive some data simultaneously.

My questions are,

1) In case of multiple slaves, does it mean, that it transfers data to many slaves, or it transfers data to one of the slaves, amidst a connection to many slave devices?

2) According to this link Figure 4, it is given that, the master keeps its SS low, until all the data it needs to send to the 3 slave devices is sent and then it makes the pin high. If so, what data & from which slave device, the master receives at the end?

3) As given in this link, in enhanced mode the load enable(LDEN) & WCOL is checked for moving next byte into the buffer. Why do we need to check them both? Isn't the WCOL sufficient for that?

4) It's given that, Master configures the clock - frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 1–100 MHz. How does the master finds the clock frequency of the slave?

5) Does the SPSR, SPCR and SPDR registers remain in both master and slave?

6) It is given that, the SPIF flag is set after the completion of transmission. If the SPIE is also enabled, then interrupt is produced. Does the flags get set in both master and slave? Does the interrupt is produced in both master and slave?

Kindly guide me. Thanks in advance.

1
embeddedmaster-slavespi
This question is 100% about hardware, so it is off-topic. You should post it at electronics.stackexchange.com - Lundin
In the example at your Maxim link, the master doesn't receive any data from the slaves. There is no signal into the Master's MISO pin. This example is one-way communication from the master to the slaves. - kkrambo
How is any answer here likely to be better than the explanation given in the link you posted? - Clifford
@kkrambo Yes, I can get that. But, my question is, the master will always receive something in return. In that link, its not like that. My doubt arised there. - Gomu
@Clifford Yes, I can get that. But, my question is, the master will always receive something in return. In that link, its not like that. My doubt arised there. - Gomu

1 Answers

1
votes

1) Any combination of one or more slaves simultaneously (on rising edge of /CS).

2) Regard the combination of slaves a one big shift register. Say each of three slaves has an eight bit register, the total being 24 bits. The master will clock out 24 bits, the first 8 will be clocked into the last slave, the second 8 to the second and the last 8 to the first slave. The data in each slave is accepted when the /CS is de-asserted (rising edge), so only those slaves that had the /CS low during the clocking of data will be affected.