Verilog dataflow delay model

Question

I am reading about Verilog data-flow programming.

I have learned about delays in data-flow model but now I have some misunderstandings about it. I found that in data-flow model, we have rejection delay model. In other words, for assign #2 c= a | b, changes can be rejected.

My question is when will the input changes be rejected?
I am sure that when a or b change so that c expected value changes, then we should start the 2 unit delay again!

My question is, do we need to start the delay again when a or b change but expected c doesn't change?

For example in a | b "a" is 0 and "b" is 1 and after sometimes we will change "a" to 1. Is there any need to reject previous time and start the 2 unit delay again for seeing the 1 in output? (note that expected c will not change because our operation is |).

Greg Greg · Accepted Answer · 2013-01-10T19:06:49

The simulator will evaluate the LHS (left hand side) of the expressions first, then apply changes the variable on the RHS (right-hand-side). Rejection (or filtering) is determined by the results of the LHS expression.

To visualize this, add an intermediate step between a | b.

assign ab = a | b;
assign #2 c = ab;

Run it thought the simulate to generate a waveform. An example output:

     0    5   10   15   20   25
     |    |    |    |    |    |
         _            _        __
a    ___/ \__________/ \______/
                  __        _____
b    _______/\___/  \______/
         _        __  _     _____
ab   ___/ \_/\___/  \/ \___/
           _        _____     ___
c    xx___/ \______/     \___/

First 2 time steps of c are unknown because there is no data for ab before time 0. The pulse on ab starting at times 7 and 15 are filtered out since they are less then 2 time steps. All other transitions in c is a shift by 2 in time ab.

There is no rejection time when a goes high at time 25 because the intermediate step (ab) does not have a transition. The simulator will do its own intermediate step, evaluating a change on a | b before deciding what action should be performed in c.

Verilog dataflow delay model

1 Answers