Further clarification as to whether interuppts are disabled in top-half handler or not

Question

Recently I came across a note in an online post that states the following:

In modern kernels, most of the differences between fast and slow interrupts have disappeared. There remains only one: fast interrupts (those that were requested with the SA_INTERRUPT flag) are executed with all other interrupts disabled on the current processor. Note that other processors can still handle interrupts, although you will never see two processors handling the same IRQ at the same time.

In other online documentation I've found statements that suggest that while handling any given interrupt, at least in the top-half handler, ALL other interrupts are disabled. This seems at odds with the quotation above. I'm most interested in the context of single CPU arm systems. Can someone enlighten me as to which of these views is correct? I should add that I'm asking in this with respect to the 2.6.10 kernel, the latest version available on the processor involved.

Likewise, help in understanding the difference between "masking" and "disabling" interrupts in Linux would be helpful. From my research it seems that masking is done in the interrupt controller (PIC) whereas disabling can be done by the CPU. Further adding to my confusion is the fact that the Linux functions disable_irq(), disable_irq_nosync() and enable_irq() seem to be related to masking, and hence the interrupt controller hardware, rather than "disabling" at the ARM CPU level. Is this correct?

Finally, I've found comments online stating that masking can NOT be done within a top-half interrupt handler. However, if this is the case, wouldn't it imply that the above-referenced function calls are not suitable for use in top-half handlers? Yet I see numerous examples online showing the use of these functions in top-half handlers.

Answer 1

First off you need to understand that this terminology is not cast in concrete -- what one group calls "A" some other group may call "B".

Generally speaking (and knowing very little about ARM, et al), the term "masking" is used when, well, a mask is set which disables some interrupts (on a bit-significant basis) while leaving others enabled. This masking naturally tends to be done in a sort of priority order (with lower priority interrupts being blocked while high priority ones are handled), and some hardware platforms implement some of the priority stuff in hardware.

"Disabling", in that context, tends to refer to blocking all interrupts, often using a different instruction from the masking instruction.

In many systems the order of operation is to immediately disable interrupts (hardware may do this automatically) when one occurs, quickly save minimal state, then rejigger the mask and re-enable, while handling the most recent interrupt.