GNU Make with several folders and files

Question

I have to write a "good" makefile for a program that has several folders: bin, inc, obj, src. Here are my make files. If I type make it just says that nothing can be done although the program is not compiled at all. Guess I have a error somewhere but I really can't find it. (ps I'm quite new to make). Thanks a lot for your help!

makefile in bin folder:

vpath %.o ../obj/
$(prog): $(objs)
$(cc) $(ccflags) -o $@ $^ $(ldflags)

makefile in obj folder:

vpath %.c ../src
vpath %.h ../inc
all: $(objs)
%.o: %.c %.h
$(cc) $(ccflags) -c $<
-include *.d

general makefile:

export prog := inv_svn
export objs := $(patsubst %.c, %.o, $(wildcard src/*.c)))
export src_dir := src
export inc_dir := inc
export obj_dir := obj
export bin_dir := bin
export cc := gcc
export ccflags := -I $(PWD)/$(inc_dir) -MMD -g -Wall
export ldflags := -lcurses -lgdbm

test := ./$(prog)

all: $(prog)
$(prog): $(bin_dir)
$(bin_dir): $(obj_dir)
$(bin_dir):
make -C $@
$(obj_dir):
make -C $@

.PHONY: clean 

clean: 
rm -f $(obj_dir)/*.[od]$(prog)

Beta Beta · Accepted Answer · 2012-10-24T19:21:12

There are too many problems here to fix all at once. Let's start small and simple, and build up.

First, you're using Make recursively when you really don't have to. Later, you should reconsider this design. For now, let's see if we can get obj/makefile working.

Second, the sub-makefiles depend on variables (like objs) passed down from the invoking makefile, variables which they could just as well construct themselves. This is bad design. We'll put the assignment in obj/makefile:

objs := $(patsubst %.c, %.o, $(wildcard ../src/*.c))

(Note that I've removed an extra ) that was messing things up.)

Third, when we test this, we get ../src/foo.o ../src/bar.o, which is probably not what we want; we want to build the objects in obj/, not src/ (the assignment in the main makefile had the same problem). So we change it:

objs := $(patsubst ../src/%.c, %.o, $(wildcard ../src/*.c))

(There are more graceful ways, but never mind that for now.)

Fourth, I trust you can make similar changes to bin/makefile.

Fifth, in the main Makefile, you treat the subdirectories as targets, when they really aren't; the point of those rules isn't to construct the subdirectories, but to run Make in them. If they already exist (which they do), Make is satisfied, and concludes that $(prog) and all need not be rebuilt. We can solve this with some PHONY targets:

.PHONY: RUN_IN_$(obj_dir) RUN_IN_$(bin_dir)

$(prog):  RUN_IN_$(bin_dir)
RUN_IN_$(bin_dir): RUN_IN_$(obj_dir)
RUN_IN_$(bin_dir):
    make -C $(bin_dir)
RUN_IN_$(obj_dir):
    make -C $(obj_dir)

Crude but effective.

That should be enough to get you off the ground.

GNU Make with several folders and files

1 Answers