how to call a function in Verilog and specify parameters to it?

1
votes

How can I call a function inside a module in verilog, with the function having parameters, and define the parameters to it?

For a trivial instance:

function automatic void inv();
  parameter W = 1;
  input logic [W:0] in;
  output logic [W:0] out;

  out = ~in;

endfunction

How would I call this and define W in the call?

2
verilogsystem-verilog
In what context is the function called? We need a more complete example. - user597225
possible duplicate of Width independent functions (Solution Found) - Greg

2 Answers

1
votes

You cannot override a parameter value when calling a function. There is no syntax for this specified in the IEEE Std (1800-2009).

1
votes

As stated parameters are constant and cannot be changed after design elaboration. The dimensions are part of the data type so they also must be constant during design elaboration. If all your function calls are outside procedural contexts you might be able to get away with passing in a constant as an argument. I don't recommend doing this.