about access to pci configuration space, the macro PCI_CONF1_ADDRESS confuse me

Question

I am learning the linux kernel code,about the part of pci, and I read the file /arch/x86/pci/Direct.c, some code confuse me:

/*
* Functions for accessing PCI base (first 256 bytes) and extended
* (4096 bytes per PCI function) configuration space with type 1
* accesses.
*/
#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
(0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \
| (devfn << 8) | (reg & 0xFC))

static int pci_conf1_read(unsigned int seg, unsigned int bus,
          unsigned int devfn, int reg, int len, u32 *value)
{
unsigned long flags;

if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
    *value = -1;
    return -EINVAL;
}

spin_lock_irqsave(&pci_config_lock, flags);

outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);

switch (len) {
case 1:
    *value = inb(0xCFC + (reg & 3));
    break;
case 2:
    *value = inw(0xCFC + (reg & 2));
    break;
case 4:
    *value = inl(0xCFC);
    break;
}

spin_unlock_irqrestore(&pci_config_lock, flags);

return 0;
}

The kernel version is 2.6.18,so, the macro PCI_CONF1_ADDRESS confuse me. As you know, it can only access to the first 256-byte of the pci confiuration space when using the IO port CF8/CFC, if you want to access the space between 256~4095-byte, you must use ECAM (Enhanced Configuration Access Mechanism), but the annotation above says:

extended (4096 bytes per PCI function) configuration space with type 1 accesses.

Does this mean that it can access all the 4096-byte of the pci configuration space when using IO port CF8/CFC? But why does the PCI LOCAL BUS SPECIFICATION never mention this?

Meanwhile,i also feel puzzled about the expression:

((reg & 0xF00) << 16)

It use this way to generate a pci config address,I never saw this expression in any book or SPECIFICATION.

user2303463 user2303463 · Accepted Answer · 2013-04-21T01:48:41

This is non standard feature of AMD CPUs and chipsets. AFAIK it won't work on Intel platform. At least from Linux kernel code I can understand that it is possible to access extended configuration space using CF8/CFC IO addresses.

patch from AMD

Regarding ((reg & 0xF00) << 16) -- looks like reserved bits 30:24 of configuration address port at CF8 used by AMD to store part of the address.

about access to pci configuration space, the macro PCI_CONF1_ADDRESS confuse me

1 Answers