Design VHDL state machine for initialization

2
votes

How do you smartest design a VHDL state machine for initializing a chip.

My current design is (in pseudo code):

....
....
case state:
when s0 =>
VHDL_CODE_FOR_WRITING_VALUE_TO_REGISTER
state := s1;
when s1 =>
VHDL_CODE_FOR_WRITING_ANOTHER_VALUE_TO_REGISTER
state := s1;
when s2 =>
DO_SOMETHING_ELSE_TO_FINISH_INIT
....
....
end case;

The code in s0 and s1 only differs by the value that is written to the register.

This made me think that there must be a smarter way (which is still Synthesize able)?

What made me think something can be done more clever, is the phrase "Don't repeat yourself", but I'm not sure this applies to VHDL.

2
vhdl

2 Answers

3
votes

If you have common assignments in states s0 and s1, pull it out of the case statement.

case state:
when s0 =>    
    a <= '0';
    b <= '1';
    c <= '0';
    nextState <= s1;
when s1 =>    
    a <= '0';
    b <= '1';
    c <= '1';
    nextState <= s2;
when s2 =>    
    a <= '1';
    b <= '0';
    c <= '1';
endcase;

...would become...

a <= '0';
b <= '1';
c <= '1';

case state:
when s0 =>    
    c <= '0';
    nextState <= s1;
when s1 =>    
    nextState <= s2;
when s2 =>    
    a <= '1';
    b <= '0';
endcase;

...or if that isn't suitable, pull the code into a function and call that in each case.

There's nothing VHDL specific about this though.

2
votes

Although the continuous refrain of VHDL answerers (including me) is "think hardware, not software", this time the software thought process is the one that serves you well :)

The usual don't repeat yourself(DRY) solution is to encapsulate the behaviour you want in a function or procedure. You can do just this in VHDL and any competent tool will be fine with it.