SystemVerilog randc reinitialization

Question

I was wondering if there is a way to reinitialize a randc variable. I am trying to set several registers, but need to make sure they can be set in arbitrary order. This object may get re-randomized (there are some other random values in the class), and then the function may get called again. My code looks something like this:

typedef enum bit[N:0] { REG1, REG2, REG3, REG4, ... } reg_order_e;
local randc reg_order_e reg_order;

function void set_regs();
    repeat( reg_order.num() ) begin
        case( reg_order )
            REG1: set_reg1();
            REG2: set_reg2();
            REG3: set_reg3();
            REG4: set_reg4();
        endcase
        assert(randomize( reg_order ));
    end
endfunction : set_regs

Alternatively, is there a way of calling std::randomize() on a variable to make it a randc? Thanks, -Tim

What problem are you seeing with your current code? It should properly iterate over all values in reg_order_e in a randc manner. — dwikle
How would the randsequence guarantee that every register gets hit? — Tim

Tim Tim · Accepted Answer · 2012-08-10T15:25:14

I found the solution based on some comments on the verification academy forum where I posted the same question. Basically, to achieve what I want, I need to create a new class with its own random variable

class helper;
     randc reg_order_e reg_order;
endclass : helper

task do_some_work();
    helper helper_inst = new();
    repeat( reg_order_e.num() ) begin
        assert( helper_inst.randomize() );
        case( helper_inst.reg_order )
            REG1: ...
            REG2: ...
        endcase
    end
endtask : do_some_work

SystemVerilog randc reinitialization

1 Answers