1
votes

Given the code :

void transpose2(array dst,array src)
{
  int i,j;
  for ( i=0; i<4; i++) {
    for ( j=0; j<4; j++) {
     dst[i][j] = src[j][i];
    }
  }
}

Assumptions :

  • int is 4 bytes

  • src array starts at address 0 , dst starts at address 64

  • the size of the cache is 32 bytes , at the beginning the cache is empty

Assuming that I have a cache with size of 32 bytes , under write through ,write allocate & LRU , using 2way set associative method , where each block is 8 bytes :

When I read from the memory , how many bytes do I take each iteration from the memory ?

is it 4 or 8 ?

What I'm quite sure about is that the cache has 4 cells , or rows , and each row has 8 bytes .Is this correct ?

What is a little confusing is the 2way part , I think that each way has 4 bytes , right ? please correct me if I'm wrong ...

Then when I "take" a block from the memory , I just don't exactly understand how many bytes !!?

Thanks in advance

Ron

2
Is this homework or just self-learning/curiosity? 32-byte caches don't exist.Mysticial
@Mysticial: This is no homework , this is an exercise before an exam that I'm going to have in the following week .JAN

2 Answers

3
votes

The cache way (aka its associativity) does not affect the amount of data that's transferred when a transfer occurs; the block size is the block size.

Associativity is simply a measure how many possible locations there are in the cache that a given block from memory could be stored. So:

  • For a direct-mapped cache (associativity=1), memory address xyz will always map to the same cache location.
  • For a two-way cache, xyz could map to either of two cache locations.
  • For a fully-associative cache, xyz could map to anywhere in cache.

I'm really not saying anything here which isn't already explained at e.g. Wikipedia: http://en.wikipedia.org/wiki/CPU_cache#Associativity.

0
votes

When the CPU references (load or store) a word from a block that is not in the cache, that block is demanded to memory. So, with the parameters supplied, every cache miss involves a 8 byte transfer from memory to cache.

Related to the terminology, your cache has 4 entries, containers or cache lines (32 bytes / 8 bytes/block). As it is 2-way associative, there are 2 sets of 2 entries. Blocks with even addreses map to set 0, while blocks with odd addresses map to set 1.

Block addresses are obtained by shifting the word address log2(block_size) bits (3 bits in your cache). For example:

  • address 64 belongs to block 8
  • address 72 belongs to block 9