I want to much more clear about why we use register and buffer register use in program control unit or other places. I know buffer register to store data temporarily to help processor to do other work.
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If the CPU is prefetching the next instruction while it still needs the control signals from the previous, that could explain having an IBR separate from an IR. If not, I don't see an obvious reason. Of course this whole model is a very simplistic CPU (probably not pipelined at all); see Does any computer resemble the model taught in UK secondary education? for details on how it's simplified for teaching, and has redundancies like this. Not sure if your diagram is exactly that UK model or not; where's it from?
– Peter Cordes
The IBR/IR are separate from the MBR so that the instruction currently executing can access data (read or write) which will change the MBR. The prefetching and buffering in IBR might be also be in support of variable length instructions -- as the IBR has a path to the MAR it may be an address byte (or word), i.e. the second byte (or word) of some 2 byte (or 2 word) instruction.
– Erik Eidt
On another note, it is weird though that the ALU has direct access to the MBR but not to the MAR. Suffice it to say, perhaps, that these are teaching materials.
– Erik Eidt
