So below is my priority circuit module
module prm (input logic D, A, E, F,
output logic [3:0] y);
always_comb
if (D) y = 4'b1000;
else if (A) y = 4'b0100;
else if (E) y = 4'b0010;
else if (F) y = 4'b0001;
else y = 4'b0000;
endmodule
and I need its output to be linked with the input of seven segment module
module segprm (input logic [3:0] y,
output logic [6:0] seg);
prm prm1 (.y(y));
always_comb
case (y)
1000: seg = 7'b000_0000;
0100: seg = 7'b100_1100;
0010: seg = 7'b000_0110;
0001: seg = 7'b100_1111;
default: seg = 7'b111_1111;
endcase
endmodule
My thought was to create an instance and link output y of prm to input y of segprm using ports
prm prm1 (.y(y));
but I get these errors and I can't think any other way to connect these modules together
Error (12014): Net "y[3]", which fans out to "Equal0", cannot be assigned more than one value
Error (12015): Net is fed by "prm:prm1|y[3]"
Error (12015): Net is fed by "y[3]"
Error (12014): Net "y[2]", which fans out to "Equal0", cannot be assigned more than one value
Error (12015): Net is fed by "prm:prm1|y[2]"
Error (12015): Net is fed by "y[2]"
Error (12014): Net "y[1]", which fans out to "Equal0", cannot be assigned more than one value
Error (12015): Net is fed by "prm:prm1|y[1]"
Error (12015): Net is fed by "y[1]"
Error (12014): Net "y[0]", which fans out to "Equal0", cannot be assigned more than one value
Error (12015): Net is fed by "prm:prm1|y[0]"
Error (12015): Net is fed by "y[0]"
Note1: I'm using Quartus Prime Lite Edition
Note2: I must use only prm and for top level hierarchy segprm