0
votes

So below is my priority circuit module

module  prm (input  logic                   D,  A,  E,  F,
             output logic       [3:0]                   y);
    
    always_comb
        
        if      (D) y   =   4'b1000;
        else if (A) y   =   4'b0100;
        else if (E) y   =   4'b0010;
        else if (F) y   =   4'b0001;
        else        y   =   4'b0000;
        
endmodule

and I need its output to be linked with the input of seven segment module

module  segprm  (input  logic       [3:0]       y,
                 output logic       [6:0]       seg);
                         
    prm prm1 (.y(y));
    
    always_comb
        
        case    (y)
        
            1000:   seg =   7'b000_0000;
            0100:   seg =   7'b100_1100;
            0010:   seg =   7'b000_0110;
            0001:   seg =   7'b100_1111;
            
            default:    seg =   7'b111_1111;
            
        endcase
        
endmodule

My thought was to create an instance and link output y of prm to input y of segprm using ports

prm prm1 (.y(y));

but I get these errors and I can't think any other way to connect these modules together

Error (12014): Net "y[3]", which fans out to "Equal0", cannot be assigned more than one value

Error (12015): Net is fed by "prm:prm1|y[3]"

Error (12015): Net is fed by "y[3]"

Error (12014): Net "y[2]", which fans out to "Equal0", cannot be assigned more than one value

Error (12015): Net is fed by "prm:prm1|y[2]"

Error (12015): Net is fed by "y[2]"

Error (12014): Net "y[1]", which fans out to "Equal0", cannot be assigned more than one value

Error (12015): Net is fed by "prm:prm1|y[1]"

Error (12015): Net is fed by "y[1]"

Error (12014): Net "y[0]", which fans out to "Equal0", cannot be assigned more than one value

Error (12015): Net is fed by "prm:prm1|y[0]"

Error (12015): Net is fed by "y[0]"

Note1: I'm using Quartus Prime Lite Edition

Note2: I must use only prm and for top level hierarchy segprm

2

2 Answers

1
votes

You can connect these modules together inside another module. For example:

module  chip    (input  logic                   D,  A,  E,  F,
                 output logic       [6:0]       seg);

logic [3:0] y;

prm prm1 (
    .A  (A),
    .D  (D),
    .E  (E),
    .F  (F),
    .y  (y)
);

segprm segprm (
    .y    (y),
    .seg  (seg)
);
endmodule

You would then remove the prm1 instance from the segprm module.


Another approach is to add more input ports to segprm and keep the prm instance inside segprm.


Also, I think you have an error in the segprm module. I think you meant to use a 4'b prefix for the case items:

        4'b1000:   seg =   7'b000_0000;
        4'b0100:   seg =   7'b100_1100;
        4'b0010:   seg =   7'b000_0110;
        4'b0001:   seg =   7'b100_1111;
-1
votes

It seems solution is to create an instance into segprm in which you link every input of prm to every bit of the input of segprm using ports. Of course the output of prm is not connected anywhere so it will show a connectivity warning but that's not a big deal, at least in this situation.

prm prm1 (.D(y[3]), .A(y[2]), .E(y[1]), .F(y[0]));