VHDL syntax error using with-select statement

Question

I am writing a code for a seven segment decoder for a project yet when I check for syntax errors it shown me those:

Error (10500): VHDL syntax error at sevenseg.vhd(16) near text "with"; expecting "end", or "(", or an identifier ("with" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at sevenseg.vhd(17) near text "when"; expecting ";"

My code:

library IEEE;
use IEEE.std_logic_1164.all;

entity sevenseg is
    port (m3, m2, m1, m0:in std_logic;
            out7 : out std_logic_vector (6 downto 0));
end sevenseg;

architecture ssdec of sevenseg is
    signal min : std_logic_vector (3 downto 0);
begin
    process(m0, m1, m2, m3)
begin
    min <= m3 & m2 & m1 & m0; --concatenate m0, m1, m2, m3 into vector min
    
    with min select                                 --here is where the error specify
    out7    <=  "0111111"   when "0000" | "1010",   -- 0 
                "0000110"   when "0001" | "1011",   -- 1
                "1010111"   when "0010" | "1100",   -- 2
                "1001111"   when "0011" | "1101",   -- 3
                "1100110"   when "0100" | "1110",   -- 4
                "1101101"   when "0101" | "1111",   -- 5
                "1111100"   when "0110",            -- 6
                "0000111"   when "0111",            -- 7
                "1111111"   when "1000",            -- 8
                "1100111"   when "1001";            -- 9

end process;
end ssdec;

What are the errors and how I correct it, thanks.

It's called a selected signal assignment. See IEEE Std 1076-2008 10. Sequential statements, 10.5 Signal assignment statements, 10.5.4 Selected signal assignments. Before revision -2008 Selected signal assignment was only available as a concurrent statement (e.g. -2002 9 Concurrent statements, 9.5 Concurrent signal assignment statements, 9.5.2 Selected signal assignments). Also see -2008 11.6 Concurrent signal assignment statements. — user1155120

Tricky Tricky · Accepted Answer · 2021-03-25T11:48:27

In VHDL versions prior to 2008, with..select statements can only be used outside of a process. So to fix the error, either:

move the with..select outside of the process
Use VHDL 2008 or later

If you go with 2. above you will also need to add min to the process sensitivity list.

You also have an issue that there is no "others" choice in the with..select. ALL cases must be covered in a with..select. Because min is a std_logic_vector, you must cover all combinations of all of the 9 idividual state types. Hence when others is usually the best way to cover everything.

VHDL syntax error using with-select statement

1 Answers