How to print system verilog coverage bin value at end of simulation?

Question

I want to find out how many times the state machine went through the following sequence of states by displaying the count at the end of the simulation.

I could not find a way to dump the value of the bin "b" in the code below.

interface i;
typedef enum { S0, S1, S2, S3} state_e;
state_e  state;
assign state = dut1.sm_state;

covergroup my_cg @(state);
    coverpoint state {
        bins b = (S0 => S1 => S2 => S3);
    }
endgroup
my_cg cg1 = new();

final begin
    $display("COVERAGE:CG1.state:%0d", cg1.state.get_coverage());
end

endinterface

Currently the output gives 100 if the sm went through the arc even once. I would instead like the count how many times it went through the arc.

dave_59 dave_59 · Accepted Answer · 2019-06-29T20:22:51

get_coverage does not give you a count of bin hits—it only gives you the percent of bins hit, or the ratio of bins hit to the total number of bins. For performance, most tools stop counting after the bin has met its required minimum hits, just 1 hit by default. This saves not only the counting, but also evaluating the set of selection expressions that determine which bin to hit.

For debug, most tools give you a way of reporting the actual bin hit counts for the entire simulation.

How to print system verilog coverage bin value at end of simulation?

1 Answers