Asking about FPGA design with IP cores

Question

I am new to Verilog, also FPGA, and currently working on the project involved them. I am conducting channel coding blocks for a broadcast standard DVB-S2 including BCH encoder, scrambler and BBheader insertion. I'm using Vivado 2015.4 for hardware design and Zynq-7000 ZC702 evaluation kit, and I wonder:

1. Is it necessary to connect my IP cores which are the blocks with the Processing unit(for Vivado 2015.4 is ZynQ-7000) for implementation?
2. Do I have to generate the bit stream to export it to SDK for software developing. I really don't know what is the purpose for exporting to SDK when you all have designed your IP on Vivado.
3. Can anyone give me an example flow of designing a BBheader insertion(which is more like adding the flags bits in front of the desired data for recognition).

What I just want is to read the data from Block ROM and encode those data (which is video but then converted into bin or hex file) with my IP cores.

Answer 1

1) If you intend to make use of the processor to run software, you need to connect it to the IP block somehow, or you'll have no way of interfacing the two.

2) Exporting the bitfile to the SDK tells the SDK which pins of the CPU are being used, which is necessary knowledge for development.

3) Though I can't give you a specific answer for this, I suggest reading the IP core documentation and it might naturally become clear.