ModelSim Verilog compiler error

0
votes

I have made a low pass filter in verilog. I have also made a testbench for it. The main verilog code seems to be compiled without any error. However, when I try to compile the testbench I encounter an error which I could not resolve it. I appreciate if anyone can help me about it.

here is the code:

module Testbench_S;

//Inputs 
reg clk;
reg clkR;
reg clk_enable;
reg en;
reg reset;
reg [7:0] filter_in;

//reg clk, reset, en;
wire [7:0] sine, cos;
reg [7:0] sine_r, cos_r;
assign sine = sine_r +(cos_r[7],cos_r[7], cos_r[7], cos_r[7:3]);
assign cos  = cos_r  -(sine[7],sine[7],sine[7],sine[7:3]);

//some other codes

endmodule

the error is as follow

Error: (vlog-13069) C:/CommonFiles/FPGA/hdlsrc/Testbench_S.v(14): near ",": syntax error, unexpected ','.

Error: (vlog-13069) C:/CommonFiles/FPGA/hdlsrc/Testbench_S.v(15): near ",": syntax error, unexpected ','.

1
syntax-errorverilog

1 Answers

1
votes

You use (cos_r[7],cos_r[7], cos_r[7], cos_r[7:3]) where you probably wanted to concatenate the bits.

The operator for concatenation is {...} (curly brackets no round brackets)