Output of multiplication in Verilog not showing in simulate behavior

Question

I've written two different Verilog snippets for combinational and sequential multiplication, which I post below. When I simulate either of the multiplications the multiplier, denoted mult_A and multiplicand, denoted mult_B show their bit-string values, but the resulting product, denoted R shows all Xs. Help in showing the codes multiplication result R would be greatly appreciated.

Combinational

module com_multiplication(mult_A, mult_B, R);
    input [15:0] mult_A, mult_B;
    output R;

    reg [31:0] R;

    integer k;

    always@(mult_A, mult_B)
    begin
    R = 0;
    for(k = 0; k < 16; k = k + 1)
        if(mult_A[k] == 1'b1) R = R + (mult_B << 1);
    end
 endmodule

Serial

module ser_multiplication(mult_A, mult_B, clk, start, R, finish);
    input [15:0] mult_A, mult_B;
    input clk, start;
    output R, finish;

    reg [31:0] R;
    reg [15:0] mult_A_duplicate;
    reg [31:0] mult_B_duplicate;
    reg [4:0] p;
    wire finish = !p;

    initial p = 0;

    always@(posedge clk)
      if (finish && start) begin
        p = 16;
        R = 0;
        mult_B_duplicate = {16'd0, mult_B};
        mult_A_duplicate = mult_A;

      end else if (p) begin
         if (mult_A_duplicate[0] == 1'b1) R = R + mult_B_duplicate;
            mult_A_duplicate = mult_A_duplicate >> 1;
            mult_B_duplicate = mult_B_duplicate << 1;
            p = p - 1;
      end
endmodule

Testbench

For now the serial part is commented out.

module multiplication_tb; 
  reg clk, start, finish; 
  reg [15:0] mult_A,  mult_B;
  reg [31:0] R; 

  com_multiplication U0 (  
  .mult_A                   (mult_A),
  .mult_B                   (mult_B),
  .R                        (R) 
  ); 

  /*ser_multiplication U1 (  
  .clk                      (clk),
  .start                        (start),
  .finish                   (finish),
  .mult_A                   (mult_A),
  .mult_B                   (mult_B),
  .R                        (R)
  ); */


  initial 
  begin 
  $display("time\t clk start finish");  
  $monitor ("%g\t %b %b %b %b %b %b", $time, clk, start, finish, mult_A, 
mult_B, R);
    #100     clk = 0; 
    mult_A =0;
    mult_B = 0;
    #10 mult_A = 2;
    mult_B = 3;
   #20 mult_B=2;

   #10 mult_B=5;
   #100 $finish;
 end 

 always 
 #5 clk = !clk; 

endmodule

Oldfart Oldfart · Accepted Answer · 2018-03-02T09:22:52

I just glanced at your code but it looks like your clock is not toggling. Simple way to make a forever toggling clock is:

initial
begin
   clk = 1'b0;
   forever
     #50 clk = ~clk;
end

Output of multiplication in Verilog not showing in simulate behavior

1 Answers