CPU frequency and rising edge count

Question

I am confused about CPU clock speed.

I thought I had a solid understanding of after watching this YouTube video, and reading this web page, but when I returned to a VHDL tutorial on Pluralsight (link not given as it is not free) that talks about clock speed, I am not sure.

Please consider the following code which is designed to be a very simple timer:

entity boardio is
  port (
    clock_50: in bit;
     hex0 : out bit_vector(0 to 6);
     hex1 : out bit_vector(0 to 6);
     hex2 : out bit_vector(0 to 6);
     hex3 : out bit_vector(0 to 6);
     key : in bit_vector(0 to 3);
     sw: bit_vector(0 to 9);
     ledr: buffer bit_vector (0 to 9)
  );
end boardio;

architecture arch of boardio is
signal count : integer := 1; -- not a variable!
signal clock_1hz : bit := '0';
signal mins, secs : integer range 0 to 59 := 0;

function hex_digit(x:integer; constant hide_zero:boolean := false) return bit_vector is
begin
    case x is
        when 0 => 
            if hide_zero then
                return "1111111";
            else
                return "0000001";
            end if;
        when 1 => return "1001111";
        when 2 => return "0010010";
        when 3 => return "0000110";
        when 4 => return "1001100";
        when 5 => return "0100100";
        when 6 => return "0100000";
        when 7 => return "0001111";
        when 8 => return "0000000";
        when 9 => return "0000100";
        when others => return "1111111";
    end case;
end function;

begin

-- 1hz clock
-- ****************************************************
process(clock_50)
begin
    if (clock_50'event and clock_50 = '1') then
        count <= count + 1;
        if (count = 25000000) then -- half the rate
            clock_1hz <= not clock_1hz;
            count <= 1;
        end if;
    end if;
end process;
-- ****************************************************
process(clock_1hz, key)
begin
    -- update # of seconds
    if (clock_1hz'event and clock_1hz = '1') then
        if (key(0) = '0') then
            secs <= 0;
            mins <= 0;
        else
            if (secs = 59) then
                mins <= (mins + 1) rem 60;
            end if;
            secs <= (secs + 1) rem 60;
        end if;
    end if;
end process;

process(clock_1hz)
begin
        hex0 <= hex_digit(secs rem 10);
        hex1 <= hex_digit(secs / 10, true);
        hex2 <= hex_digit(mins rem 10, mins = 0);
        hex3 <= hex_digit(mins / 10, true);
end process;

end arch;

I have posted all the code so everyone has the full context, but the bit I'm really interested in is the 1hz clock process I've indicated with asterisks.

It suggests that in one second of a 50MHz clock there will be 250,000,000 rising edges in one second. However, the video and web page I linked to suggest that for a 1hz clock there will be one rising edge and one falling edge in one second, so it follows that there would be 500,000,000 of each for a 50Mhz clock.

Can someone please clarify what CPU frequency actually means in terms of rising edges and falling edges please, along with 'tick' ? Diagrams would be much appreciated, as I'm no longer sure the ones on my link are correct...

Use std_ulogic and std_logic types, not bit. Use downto for you vector for correct orientation. Constrain your integers. E.g. signal count : integer range 0 to 25000000 := 1. Remove key form the second process sensitivity list. Finally: a division takes up A LOT of resources and are quite slow. Try do design your code without these rem and divisions. — JHBonarius
Note the mistake in the sensitivity list for that process (it won't affect the issue though). Note also the difference between 25000000 and 250,000,000. Note also you need no execute clock_1hz <= not clock_1hz; TWICE to get another rising edge. Put these together and you'll see there are 50 million rising edges per second on a 50MHz clock, exactly as there should be. And that's the second piece of garbage you posted from that site ... whatever you paid for it, it's too much. — user_1818839
There are 50 million rising edges in a one second interval of a 50 MHz clock. The code has the right number of zeros, you keep adding an extra zero in your written description and comments. — user1155120
There's also a comment saying -- half the rate in your code. 50MHz clock generates 50000000 rising edges in 1 second (definition of Hz). This code negates the clock_1hz signal when counter reaches 25000000 rising edges (Half the rate of 50MHz) thus creating an edge every half second (or rising edge every second). — Vinay Madapura

DLnd DLnd · Accepted Answer · 2018-01-12T08:09:39

A frequency of x Hz means you have x entire periods of the signal per second. If you have a typical rectangular clock signal, this means x rising edges and x falling edges per second. On a 1 Hz clock, you have one rising and one falling edge per second, giving a full period. On a 50 MHz clock(50 million Hertz) you have 50 million rising and falling edges.

In order to generate a 1 Hz clock from a 50 MHz clock, you need to reduce the period of the clock by a factor of 50 Million. However, since each clock cycle contains a rising and a falling edge, you need to change your output clock signal twice per period(i.e. twice per second). Thus, the counter in your example counts to 25 million(not 250 million as you wrote, look closely at the code!), then inverts the output signal. This generates one falling and one rising edge per second, each half a second apart, which is exactly what you usually want - a signal that repeats once per second and is divided evenly between 'on'-state and 'off'-state, which is called a 50% duty cycle. Your clock really doesn't need a 50% duty cycle to work well, because clocked logic uses edges rather than the clock state, but if the 'on' or 'off'-pulse of the clock gets too short, logic might not detect it correctly and bug out.

A tick is one clock period, so a 50 MHz clock will generate 50 million ticks per second.

CPU frequency and rising edge count

1 Answers