formal size has no actual or default value vhdl

Question

I'm trying to simulate a program on xilinx vivado suite, which intends to find the square of a given integer. Part of my program-

for j in (num_of_bits-1) downto 0 loop 
    res <=res+to_integer(unsigned(dvandha(shln(std_logic_vector(to_unsigned(num)),j)))); -- I get error here
    report "The resulting square is " & integer'image(res);
    res <= to_integer(unsigned(shln(std_logic_vector(to_unsigned(res)),1))); --I get error here
end loop ;

Here 'res' is inout of integer type. dvandha is a function I wrote. It's input parameters are std_logic_vector and integer. shln is shift left function with 'n' shifts. num is my integer input. I'm getting the following error -

"formal size has no actual or default value "

I am not getting any idea what the error is and how to get rid of this. I have not used any variable/signal by name "size" in my program. what is the size it is pointing me out? I suppose it is the error with typeconversion. I used 'numeric_std' library for type conversion. Please help! thanks in advance.

Tip: next time don't inline everything. A) that makes it hard to read, B) it makes it easier to make an error. — JHBonarius

Staszek Staszek · Accepted Answer · 2017-06-14T16:56:10

You need to add size parameter to to_unsigned function, probably like this:

for j in (num_of_bits-1) downto 0 loop 
    res <=res+to_integer(unsigned(dvandha(shln(std_logic_vector(to_unsigned(num,j)),j))));
    report "The resulting square is " & integer'image(res);
    res <= to_integer(unsigned(shln(std_logic_vector(to_unsigned(res,1)),1))); 
end loop ;

size refers to the size of vector in to_unsigned function.

formal size has no actual or default value vhdl

1 Answers