UVM TB components to be used

0
votes

I have a verification tb structure for a parity encoder decoder like shown below where I am driving data in to the Encoder, getting the output, adding randomised error to it and passing it as input to the Decoder.

My question is do I need two drivers to drive 1)Data_in_08p and 2) Data_corrupted_in? I should have a component that creates random error at random positions and xor's it with the Data_out_08p. What should be the nature of thsi component i.e should it be a driver? Can I have two drivers in 1 agent or do I need to create two agents here?

To be precise, how we define our driver/env when one input of DUT depends upon a DUT output? How many sequences and sequencers and monitors will be there?

1
system-veriloguvm
Can't you verify both encoder & decoder separately? Why are you making common testbench to verify 2 different blocks? - Karan Shah

1 Answers

1
votes

The block diagram for the UVM testbench that would be required in order to verify the DUT would probably be something like this:

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In UVM terms, you would require the following agents:

  1. One active agent to send transactions to the input of the encoder block.
  2. One passive agent to capture transactions at the output of the encoder block.
  3. One reactive agent to send transactions to the input of the decoder block.
  4. One passive agent to capture transactions at the output of the decoder block.

Please notice that the monitor sitting on the encoder output agent will capture the transactions and send them through an analysis port to the sequencer that is sitting on the decoder input agent. This is called a "reactive" agent because it waits until something has been received in order to generate a transaction. You will then inject errors from the sequence that is running on the decoder input agent's sequencer.

Verilab has a very good paper that talks in details about "Reactive Agents": http://www.verilab.com/files/mastering_reactive_slaves.pdf