What is relation between Status register and Control register?

Question

While going through Basic I/O in Computer organisation by "carl hamacher" ,i am confused with lots of terminologies.

In Interrupt I/O,Whenever a device raise an interrupt ,Processor Interrupts the program currently being Executed and saves the content Of Program Counter and Status register and then Interrupt is being processed by ISR.Upon completion of ISR ,the return from execution instruction is executed and then the saved status register and PC are restored.It is perfectly clear to me .

But i am stuck in the following points...-:

there is a flag IE (interrupt enable) ,if it is 1 then Interrupt req from I/O device are accepted .

On the other hand there is one more point .

The interface of an I/O device includes a control register that contains the information that governs the mode of operation of the device. One bit in this register may be dedicated to interrupt control. The I/O device is allowed to raise interrupt requests only when this bit is set to 1

Now what is this control register and which bit they are talking about ? is it different than IE flag??? what is relation between Status register and Control register?

Additionally there is one more point

The information needed to determine whether a device is requesting an interrupt is available in its status register. When the device raises an interrupt request, it sets to 1 a bit in its status register, which we will call the IRQ bit. The simplest way to identify the interrupting device is to have the interrupt-service routine poll all I/O devices in the system. The first device encountered with its IRQ bit set to 1 is the device that should be serviced. An appropriate subroutine is then called to provide the requested service

Please explain relation between these 3 bits i.e IE,IRQ and control register's bit I am totally confused..!!!

Margaret Bloom Margaret Bloom · Accepted Answer · 2017-01-04T09:23:19

Consider this simplified, yet complete, view of the CPU logic behind acknowledging interrupts:

The IE flag in the Status register is used to mask off all the interrupt requests from the IRQ pin.
It controls whenever the CPU will process an interrupt when IRQ is asserted.
This status register is in the CPU.

Now consider this simplified view of a device:

The device has a control block that recognises when to generate an interrupt request (the Interrupt generation logic in the scheme).
This block outputs a signal to request an interrupt (IRQreq) and a set of n signals that identify the source/reason of the interrupt (for example, transmission buffer empty vs new data received).

Both these signal will end in the device status register but the IRQreq can be eventually masked through a device control register bit IRQen.

If IRQen is zero, the device IRQ pin will be zero too and no IRQ is requested, furthermore, no bit is set in the status register to indicate that an interrupt has been requested.
The interrupt reason is still written though because the software can use polling to test the device status.

The same ISR can be used to handle multiple devices, so recognising which device actually triggered it is necessary and this is done by inspecting each possible device status register.

So there are three registers:

CPU status register Let the software mask interrupts at the CPU level; all interrupts are masked, no matter what device generates them.
Device control register Let the software mask interrupts per device; some device can be prevented from generating an interrupt some not.
Device status register Let the software know about the last generated interrupt (if any). Usually, this is also used to ACK the interrupt.

What is relation between Status register and Control register?

2 Answers