VHDL - Qualified Expression must match the type that is implied for the expression by context

Question

This question is a continuation to my last question.

As I mentioned before, I'm trying to interface to a classic HD44780 LCD. I have implemented local ram to which I write the data I wish to show up on the display.

The ram is defined this way (slight change from last question):

type ram_type is array (integer range <>) of std_logic_vector(7 downto 0);
signal lcd_mem : ram_type(0 to 16*2-1);

I would like to display a bunch of constant characters and a number in a certain location on the LCD, I tried doing this by writing directly to lcd_mem this way:

lcd_mem <= (0 => x"45", 1 => x"72", 2 => x"72", 3 => x"6F", 4 => x"72", 5 => x"73", 6 => x"3A", 15 => x"30",    16 => x"54", 17 => x"58", 18 => x"3A", 30 => x"4D", 31 => x"3A", others => x"20");

Line 79:

lcd_mem(22 to 28) <= get_ascii(1234567); --to_integer(unsigned(n_bits(39 downto 20)))

the integer 1234567 will later be replaced by the to_integer comment.

I have written the get_ascii function which is supposed to convert the integer into bcd representation and than to ascii by adding 0x30 to the bcd representation. Here is a part of the function:

variable num    : ram_type(0 to 16*2-1);
variable temp   : std_logic_vector(number'range);
variable bcd    : unsigned ((4*7-1) downto 0) := (others => '0');
.
.
.
num(0) := std_logic_vector(bcd(3 downto 0) + x"30");
num(1) := std_logic_vector(bcd(7 downto 4) + x"30");
num(2) := std_logic_vector(bcd(11 downto 8) + x"30");
num(3) := std_logic_vector(bcd(15 downto 12) + x"30");
num(4) := std_logic_vector(bcd(19 downto 16) + x"30");
num(5) := std_logic_vector(bcd(23 downto 20) + x"30");
num(6) := std_logic_vector(bcd(27 downto 24) + x"30");          
return num;

When compiling I'm getting the following error:

Error (10511): VHDL Qualified Expression error at display_ber.vhd(79): get_ascii type specified in Qualified Expression must match ram_type type that is implied for expression by context

I can't quiet understand the meaning of the message. I have tried defining a shorter variable of ram_type(0 to 6) to receive the value from the get_ascii function but that didn't help.

Perhaps a Minimal, Complete, and Verifiable example? Neither line 79 is discernible nor is any qualified expression. — user1155120
Okay, that's line 79. Where's the qualified expression? And note the purpose of Complete in an MCVe is to allow the reader (and answerer) to "reproduce the problem". — user1155120
The syntax is qualified_expression ::= type_mark ' ( expression ) | type_mark ' aggregate, we see neither of those here (a type mark is either the name of a declared type or subtype, the apostrophe is a required element of the production. See IEEE Std 1076-2008 9.3.5 Qualified expressions. Also the past participle of 'write' is 'written'. Something along the lines of "I have written the get_ascii function which is supposed to...". — user1155120
Declaring num to have a range to match the number of bcd 'digits' is the correct thing to do, noting that an integer has - 231 -1 to 231 -1 as a minimum range, (–2147483647 to +2147483647 which fits in 10 digits plus a perhaps optional sign). You can slice the value returned by a function, the assignment with static index ranges for the target and expression slices can be dependent on the first character (the sign) or leading zeros. — user1155120

Mike Mike · Accepted Answer · 2016-05-28T20:47:13

Ok, apparently this happen because I defined the type "ram_type" in both the package and the architecture.

After deleting the "ram_type" definition in the architecture the error is gone.

VHDL - Qualified Expression must match the type that is implied for the expression by context

1 Answers