5
votes

I'm trying to learn about MIPS pipe-lining and the hazards associated to them. I'm having trouble picturing what a structural hazard looks like in MIPS instructions.

I've read that it is a situation where two (or more) instructions require the use of a given hardware resource at the same time. And I've seen examples shown in clock cycles before. But can anyone just provide a simple MIPS instruction set example for me to see? I'm having difficulty finding one online. Just see lots of examples for data hazards and that's not what I'm looking for. Thanks!

2

2 Answers

5
votes

It is hard for you to come by this problem because it's usually resolved in the HW architecture...

Here are two examples:

  1. Assume a write is made to the register file (RF) during stage 5 (WB) and a read is made to the same register on the RF on stage 2 (ID) at the same time. This is a structural hazard because two instructions are trying to access the same resource at the same clock cycle (what value will be read?). This can be resolved (in the HW), for instance, by splitting the RF access to two clock phases, write on HIGH and read on LOW. Moreover, if you think about it, a structural hazard is why there are separate 2 read ports and 1 write port in the RF.

  2. Assume an instruction is being fetch from memory (stage 1, IF) and another read/write is done to the memory on stage 4 (MEM). Again, same resource accessed on the same cycle. This was resolved by separating the data and instruction memories (harvard architecture). It may look obvious to you but you can lookup Princeton Architecture and see an example to a unified memory.

So if we take the first example for instance: any set of instructions with a load (lw) command to the same register as in a R-type command (like add) that follows after two other instructions will do the trick:

lw $8, 100($9)
add $10, $11, $12
add $10, $11, $12
add $10, $8, $12

Hope that helps.

0
votes

This might work, but I'm not a big MIPS person:

add $t0, $t1, $t2 
sw  $t3, 0($t4)
sub $t5, $t6, $t7
sub $t8, $t9, $t0
sw  $t0, 0($s0)