(VHDL) signal <CLK_IBUF> is incomplete. The signal does not drive any load pins in the design

Question

Hi awesome stackoverflow community,

I'm working on a project for my school and I have to switch on different leds one after another one to make a "rotating light" on a Xilinx Spartan3E-100. Currently, my VHDL program works but with no clock so all the leds are switched on (too fast). When I try to add clock, I get the following error:

The signal <CLK_IBUF> is incomplete. The signal does not drive any load pins in the design.

Here's my VHDL code (edited):

  library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test2 is
    Port ( CLK : in  STD_LOGIC;
           S0 : out  STD_LOGIC;
           S1 : out  STD_LOGIC;
           S2 : out  STD_LOGIC;
           S3 : out  STD_LOGIC;
           S4 : out  STD_LOGIC;
           S5 : out  STD_LOGIC;
           S6 : out  STD_LOGIC);
end test2;

architecture Behavioral of test2 is
CONSTANT st0 : std_logic_vector(0 TO 2) := "000"; -- listing case for signal
CONSTANT st1 : std_logic_vector(0 TO 2) := "001";
CONSTANT st2 : std_logic_vector(0 TO 2) := "010";
CONSTANT st3 : std_logic_vector(0 TO 2) := "011";
CONSTANT st4 : std_logic_vector(0 TO 2) := "100";
CONSTANT st5 : std_logic_vector(0 TO 2) := "101";
CONSTANT st6 : std_logic_vector(0 TO 2) := "110";
SIGNAL state : std_logic_vector(0 TO 2) := "000";
BEGIN
    chenillard: PROCESS(CLK)
    BEGIN
        if (rising_edge(CLK)) then -- synchronise clock for the following case
        case state is
        when st0 => -- when signal is 000
        S0<='1'; -- it will switch on a led.
        state<=st1; -- signal incrementation
        when st1 => -- when signal is 001
        S1<='1'; -- it will switch on a led.
        state<=st2; -- signal incrementation
        when st2 => -- when signal is 010
        S2<='1'; -- it will switch on a led.
        state<=st3; -- signal incrementation
        when st3 => -- when signal is 011
        S3<='1'; -- it will switch on a led.
        state<=st4; -- signal incrementation
        when st4 => -- when signal is 100
        S4<='1'; -- it will switch on a led.
        state<=st5; -- signal incrementation
        when st5 => -- when signal is 101
        S5<='1'; -- it will switch on a led.
        state<=st6; -- signal incrementation
        when st6 => -- when signal is 110
        S6<='1'; -- it will switch on a led.
        state<=st0; -- signal incrementation back to st0 for loop
        when others =>NULL;
        end case;
        end if;
    end process chenillard;
end Behavioral;

Here's my UCF file:

NET "CLK" LOC = "C8";
NET "S0" LOC= "M5";
NET "S1" LOC= "M11";
NET "S2" LOC= "P7";
NET "S3" LOC= "P6";
NET "S4" LOC= "N5";
NET "S5" LOC= "N4";
NET "S6" LOC= "P4";

I searched for answer on google but nothing that i found seems to work. thanks for help and sorry for my english, i'm not a native english speaker ;)

Try adding CLK to the process sensitivity list, and replacing wait until CLK='1' with if (rising_edge(CLK)) then ... end if;, where ... is your existing case statement. — scary_jeff
my bad @BrianDrummond i was just experimenting and forgot to erase inout when posting :) CLK is an in port. post edited. thanks for noticing — DBLJ
@scary_jeff i don't know how to add process.. i found something but not sure ;) by adding CLK to sensitivity list you mean adding CLK to the following line : chenillard: PROCESS(CLK) like this ? if so, i tried but got the same problem — DBLJ
@scary_jeff and the OP: I'm not sure if the old XST synthesizer for Spartan 3 FPGAs can handle wait until ... statements, because XST inferred an IBUF (normal input) but no IBUFG (clock input). Also your UCF file is missing the timing constraints for CLK. — Paebbels

DBLJ DBLJ · Accepted Answer · 2015-11-05T08:45:22

Finally, it works ! I noticed the truth table created by the program was different from my theoretical truth table. Here's the new truth table created by the program: Truth_table

Here's how I fixed the problem:

if (rising_edge(CLK)) then -- synchronise clock for the following case
          case state is
        when st0 => -- when signal is 000
        S0<='1'; -- it will switch on a led.
          S1<='0';
          S2<='0';
          S3<='0';
          S4<='0';
          S5<='0';
          S6<='0';
        state<=st1; -- signal incrementation
        when st1 => -- when signal is 001
        S1<='1'; -- it will switch on a led.
          S0<='0';
          S2<='0';
          S3<='0';
          S4<='0';
          S5<='0';
          S6<='0';
        state<=st2; -- signal incrementation
        when st2 => -- when signal is 010
        S2<='1'; -- it will switch on a led.
          S0<='0';
          S1<='0';
          S3<='0';
          S4<='0';
          S5<='0';
          S6<='0';
        state<=st3; -- signal incrementation
        when st3 => -- when signal is 011
        S3<='1'; -- it will switch on a led.
          S0<='0';
          S1<='0';
          S2<='0';
          S4<='0';
          S5<='0';
          S6<='0';
        state<=st4; -- signal incrementation
        when st4 => -- when signal is 100
        S4<='1'; -- it will switch on a led.
          S0<='0';
          S1<='0';
          S2<='0';
          S3<='0';
          S5<='0';
          S6<='0';
        state<=st5; -- signal incrementation
        when st5 => -- when signal is 101
        S5<='1'; -- it will switch on a led.
          S0<='0';
          S1<='0';
          S2<='0';
          S3<='0';
          S4<='0';
          S6<='0';
        state<=st6; -- signal incrementation
        when st6 => -- when signal is 110
        S6<='1'; -- it will switch on a led.
          S0<='0';
          S1<='0';
          S2<='0';
          S3<='0';
          S4<='0';
          S5<='0';
        state<=st0; -- signal incrementation back to st0 for loop
        when others =>NULL;
        end case;
        end if;
    end process chenillard;
end Behavioral;

As you can see for each case I added every LEDs which are off and not only the one led which is on. Before doing this, when ISE process mapped, it told the clk_buf were incomplete because not all the possibility were listed.

(VHDL) signal <CLK_IBUF> is incomplete. The signal does not drive any load pins in the design

1 Answers