PCI Root Complex BAR usage

0
votes

I want to understand the usage of BARs in the PCIe Root Complex. The PCIe Root Complex is already a part of the CPU (as a peripheral to it). And the CPU register spaces is easily accessible. CPU has register to access its various peripheral link PCIe controller, DIMM Controller, USB Controllers etc. So in this case what is the usage of BAR inside the PCIe RC Config space ?

Secondly I want to understand how the PCIe RC is setup during enumeration with the proper memory windows. For example lets say I have a PCIe device (EP) directly connected to the RC. And in the Config space of EP programmed with some address 'X' with some size 's'. So basically, any read/write from the CPU to the window of 'X' and 'X +s', should go to the PCIe EP. But this should go through the PCIe RC. Now how the RC knows that it should it should translate the CPU read/write to that memory window into PCIe transaction to the EP ? How does the RC is configured to do that ? Are there any standardized register in PCIe RC where this information is kept ?

/SG

1
pci-e
You should get started with the PCIe standard or the PCIe book from mindshare. The topic of how PCI configuration and enumeration works is very big and some parts are also complex. Please divide your question into smaller ones. – Paebbels

1 Answers

2
votes

The BAR (base address register) serves 2 purposes:

  1. Before enumeration it holds the requested size of the to be mapped memory.
  2. After enumeration is holds the base address (starting address) of the memory block.

A PCI endpoint (EP) can have up to 6 32-bit BARs. 2 BARs can be combined to a 64-bit BAR.

During enumeration the BIOS or the kernel traverses the PCI tree and reads the BARs and assigns the new base address.

The PCH (Platform Controller Hub / former north bridge) uses the BAR information to route data accesses to main memory or PCI EPs or whatever.

Books on PCI Express:

  1. MindShare Press - PCI Express Technology 3.0