I'm writing a testbench for a SPI interface. The interface is basically composed by four signals :
spi_clk : Signal clock provvided by the master
spi_cs : Chip select signal driven by the master
spi_miso : Input signal of the Master ( output signal of the slave)
spi_mosi : Output signal of the Master ( input signal of the slave)
I've traced the SPI Bus with an analyzer and I get file that shows every operation performed over the bus. Each operation begin with the falling edge of the chip select and it end with the rising edge os the chip select. The file is :
.................. 03fff57000000000 03fff57400000000 03fff57800000000 03fff57c00000000 02f0fffec0a3 02f0fffcfc0c 03fff54000000000 03fff54400000000 03fff54800000000 03fff54c00000000 03fff57c00000000 03f0fffc0000 03f0fffe0000 03fff55000000000 03fff55400000000 03fff55800000000 ..... and so on
Each line represents a spi operation on the bus. My problem to write the testbench is about the length of the SPI operation. It's simple to see that the byte transfered in one operation is variable. My will was to use the functions readline and hread to get the value line by line and feed my module, for example :
process
file miso_file : TEXT is in "TestBench/MISO_DATA.txt";
variable miso_line : LINE;
variable VAR_miso : std_logic_vector(63 downto 0) := (others => '0');
file mosi_file : TEXT is in "TestBench/MOSI_DATA.txt";
variable mosi_line : LINE;
variable VAR_mosi : std_logic_vector(63 downto 0) := (others => '0');
variable mosi_good : boolean;
variable miso_good : boolean;
begin
... some code ...
while not(endfile(miso_file)) loop
readline(miso_file,miso_line);
hread(miso_line,VAR_miso,miso_good);
...some code...
end loop;
wait;
end process;
This code works when the line is composed by 16 chars ( 64 bits ) but when the size is different it doesn't work. Does anyone have suggestions ?
Thanks a lot
