Can a PCIe endpoint access Root Complex BARs?

Question

I am working on an embedded PCIe system where two SoCs are connected together, the Host is a Root Complex, the Slave is an Endpoint. The Host will run Linux.

Typically the Host SoC provides memory windows, where the Endpoint BARs are mapped. This allows a card driver on the Host to read/write to IO or memory on the Slave. Often, the Slave will include a DMAC built into the PCIe IP, that works with a PCIe address and a local address. The Host will setup this DMAC by writing to the memory windows.

In my case, the Endpoint doesn't have a DMAC built in to the PCIe IP, but is does have a system DMAC. So, two questions...

1. Can an Endpoint access the Root Complex's memory via BARs?
2. Are there any performance implications of using a system DMAC instead of built in PCIe DMAC? (in other words, how do accesses via BARs appear on the PCIe bus, do you get one TLP for each access?)

Any help appreciated!

Answer 1

1. The BARs reside within the legacy confiuration space. As of such, that register can only be reached with a CfgRd or CfgWr. These TLPs (Transaction Layer Packets) can only be originated from an RC. So how would the EP know what are the valid memory addresses of the RC ? tough question, the PCI-Express specification have no answer for that. In reality there are regions that are more likely to be allocated than others, so you can make an educated guess.

2. Accessing a BAR requires at least 2 TLPs: the request (CfgWr or CfgRd) and the appropriate completion (Cpl or CplD, respectively).

I hope that helps,

Answer 2

After think about this a little, I think the answer is clear...

In my case where the Endpoint doesn't have a built in PCIe-DMAC, the Endpoint can only access RC memory using the PCIe windows. Normally, these windows are used on a RC to access EP memory (as detailed by the BARs). However, there is nothing to stop an Endpoint from using the same mechanism to access the RC memory. The only issue is one of setup. In this scenario, the RC would have to tell the Endpoint about the PCIe address and size that it should use. This is no different to the case with a PCIe-DMAC.

Answer 3

There is something called as address translation in PCIe EP. For example:

1. The host allocates the memory using malloc in virtual space.
2. The host provides the EP with the allocated virtual address through BAR.
3. Host programs the address translator as a virtual to physical translator.
4. Now when the EP generates TLPs targeted to Host virtual address, then the translator changes the DST addr (host virtual) of the TLP to the corresponding host physical address.

Source: https://patents.google.com/patent/US8171230B2/en