How to fix Xilinx ISE warning about sensitivity list?

1
votes

I synthesized my design with Xilinx ISE 13.1. Target device is Virtex 5. Then I encountered this warning:

 WARNING:Xst:819 - "F:/FRONT-END/h264/inter/src/eei/eei_mvd.vhd" 
line 539: One or more signals are missing in the process sensitivity list. 
To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. 
Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:    
<mvd_l0<3><3>>, <mvd_l0<3><2>>, <mvd_l0<3><1>>, <mvd_l0<3><0>>, <mvd_l0<2><3>>, <mvd_l0<2><2>>,
 <mvd_l0<2><1>>, <mvd_l0<2><0>>, <mvd_l0<1><3>>, <mvd_l0<1><2>>, <mvd_l0<1><1>>, <mvd_l0<1><0>>,
 <mvd_l0<0><3>>, <mvd_l0<0><2>>, <mvd_l0<0><1>>, <mvd_l0<0><0>>, <mvd_l1<3><3>>, <mvd_l1<3><2>>,
 <mvd_l1<3><1>>, <mvd_l1<3><0>>, <mvd_l1<2><3>>, <mvd_l1<2><2>>, <mvd_l1<2><1>>, <mvd_l1<2><0>>,
 <mvd_l1<1><3>>, <mvd_l1<1><2>>, <mvd_l1<1><1>>, <mvd_l1<1><0>>, <mvd_l1<0><3>>, <mvd_l1<0><2>>, 
<mvd_l1<0><1>>, <mvd_l1<0><0>>, <mvd<0>>, <mvd<1>>

Here is my source code:

proc_update_next: process(mvd_l0, mvd_l1, mvd, subMBPart_Idx, MBPart_Idx, eei_info )
  begin
    --// Init
    next_mvd_l0 <= mvd_l0;
    next_mvd_l1 <= mvd_l1;
    --// Change
    if eei_info.mb_type =  BLK_8x8 then
      for  i in 3 downto 0 loop
        for  j  in 3 downto 0  loop
          if i = to_integer(unsigned(MBPart_Idx))  and j = to_integer(unsigned(subMBPart_Idx)) then
            next_mvd_l0(i)(j)  <=  mvd(0);
            next_mvd_l1(i)(j)  <=  mvd(1);
          end  if;
        end  loop;
      end loop;
    else
      for  i in 3 downto 0 loop
        if i = to_integer(unsigned(MBPart_Idx)) then
          next_mvd_l0(i)(0)  <=  mvd(0);
          next_mvd_l1(i)(0)  <=  mvd(1);
        end  if;
      end loop;
    end if;
  end process;

Update: I change a little bit in my code and still this warning.

The mvd_l0 and mvd_l1 is two-dimension array and it appeared on sensitivity list. I know my source code is too abstract and ISE may can not understand.

I tried with Virtex 7 (not avaiable in laboratory) then there are no error. So, my question is how to fix this warning ? I can't ignore this warning because it can lead to latch.

3
vhdlxilinxsynthesis
Xilinx XST uses an old VHDL parser for older devices and a new one for new devices. Neither understands VHDL as well as users might like, so they allow you to pick the least bad, with a command line option "use_new_parser=yes" (probably also available as a tick box in the "Properties" dialog for the synthesis tool). That will let you use the new parser for old Virtex-5 devices. By the way, I hope you have verified that this code does EXACTLY what you want in simulation. If you haven't, I think you will be disappointed with what the synthesised code does. – user_1818839
@BrianDrummond: It's looked better, thank you. My design is implemented in ASIC and FPGA prototype. While the Design Compiler dont have error, Xilinx still this case. The behaviour in ModelSim is right, I'll try with sdf file later. – Khanh N. Dang
IN case of ASIC protoyping: try to synthesis it also with Vivado, the new tool of Xilinx (>=Series 7). Just to match the results and average the warning :-) – vermaete
Then you have a separate clocked process which basically copies next_mvd_* into mvd_. It is usually better style to combine the two processes into one clocked process, eliminate next_ and the big error-prone sensitivity list altogether. But given an existing working code base, I understand reluctance to do so... – user_1818839
@vermaete: Another tool is not good method, because we have an existed lincense of Xilinx now. So, I'll try it in spare time. – Khanh N. Dang

3 Answers

2
votes

Use the VHDL-2008 construct process(all) to tell the tools you want the sensitivity list to include all signals which are read.

Alternatively, make it a clocked process, only sensitive to the clock, and then you don't have to worry either.

0
votes

You should only set signals like next_mvd_l0 and next_mvd_l1 once for a set of conditions. The "init" section is still an issue. It may be better to use local variables if you are avoiding reseting the process.

Best option: add a reset to the sensitivity list and if its enabled, set next_mvd_* to your init values

--// Init
if (reset = '1') then
    next_mvd_l0 <= mvd_l0;
    next_mvd_l1 <= mvd_l1;
end if;

Second option: use a local variable

proc_update_next: process(mvd_l0, mvd_l1, mvd, subMBPart_Idx, MBPart_Idx, eei_info )
    variable mvd_10_local : 2dArrayType;
    variable mvd_11_local : 2dArrayType;
begin
    --// Init
    mvd_10_local := mvd_l0;
    mvd_11_local := mvd_l1;
    --// Change
    if eei_info.mb_type =  BLK_8x8 then
        for  i in 3 downto 0 loop
            for  j  in 3 downto 0  loop
                if i = to_integer(unsigned(MBPart_Idx))  and j = to_integer(unsigned(subMBPart_Idx)) then
                    mvd_10_local(i)(j)  :=  mvd(0);
                    mvd_11_local(i)(j)  :=  mvd(1);
                end  if;
            end  loop;
        end loop;
    else
        for  i in 3 downto 0 loop
            if i = to_integer(unsigned(MBPart_Idx)) then
                    mvd_10_local(i)(j)  :=  mvd(0);
                    mvd_11_local(i)(j)  :=  mvd(1);
            end  if;
        end loop;
    end if;
    next_mvd_l0 <= mvd_10_local;
    next_mvd_l1 <= mvd_l1_local;
end process;
0
votes

You use the VHDL record construct (eei_info.mb_type). You can add every record element to the sens-list to make xst happy. I just ignore this warning.