VHDL if statement - strange value

Question

Good afternoon,

Do you think you could explain to me what a value on the right side of the if statement means? In the example which I don't quite understand there are two declared unsigned vectors.

CONSTANT ZERO : UNSIGNED(3 DOWNTO 0) := (OTHERS=>'0); 
SIGNAL count : UNSIGNED(3 DOWNTO 0) := ZERO;

Then follows:

IF clk'EVENT AND clk='1' THEN
    if count<(2-1) THEN
         output<='1';
         etc...

What I have problems with is part

if count<(2-1)

What could this 2-1 mean? I have several ideas. From googling I found out that vector_name(n-1 downto 0) is a common way of declaring vectors, where n = number of bits OR width of the bus. However, this doesn't seem to have anything in common with the example. Another guess: the value on the left is an unsigned binary signal, so maybe 2-n means that n before comparison should be turned into a binary?

P.S. This example is from a frequency divider.

Which library declares UNSIGNED? I'm asking because I don't know if the non-standard ones provide an odd subset of what it should. Using numeric_std I can't see any good reason for not saying if count < 1. Unless it's a way of semi-documenting a kludgy fix for an unexpected off-by-one problem with the intended if count < 2, e.g. if the comparison was moved a cycle earlier to help the pipeline... — user_1818839
Here are all the libraries used: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; — petajamaja
Sorry, Mr. Drummond, could you please explain what off-by-one problem means? — petajamaja

user_1818839 user_1818839 · Accepted Answer · 2012-12-15T13:59:04

Using numeric_std I can't see any good reason for not saying if count < 1.

Perhaps it's a way of semi-documenting a kludgy fix for an unexpected off-by-one problem with the intended if count < 2, e.g. if the comparison was moved a cycle earlier to help the pipeline?

An "off-by-one" problem is also known as a fencepost problem, perhaps where the requirements were confusing. But it can also happen in a pipelined design where changes are made to the pipeline. When one stage in a pipeline is too slow, you must break off part of that stage and perform it a cycle earlier or later - without changing the final result. So if you needed to do something "when count = 2", but move it a cycle earlier, you may now need to adjust the value you are comparing "count" against.

This is not a definitive answer, you would need to consider it in the context of your actual code.

With regard to why there are two "unsigned" declarations : the first is just a named constant, which is good practice. It makes for less typing in a large design, as well as easier understanding and easier maintenance.

Even better would be:

subtype Digit is UNSIGNED(3 DOWNTO 0);
CONSTANT ZERO : Digit := (OTHERS=>'0'); 

SIGNAL count : Digit := ZERO;

and so on... then move Digit and Zero into a package and you can re-use them in all your modules.

VHDL if statement - strange value

1 Answers