adder in verilog

Question

I am designing an adder in Verilog. It will have two inputs of size N and two outputs. The first output has a size of 2N and the second has a size of K.

This is what I have so far:

module adder(
  out,
  CCR,
  inA,
  inB
);
parameter N=8,CCR_size=8;
parameter M=2*N;
input  [N-1:0]        inA,inB;
output [M-1:0]        out;
output [CCR_size-1:0] CCR;
reg    [N:0]          temp;
always @(inA or inB)
  begin
    temp      = inA+inB;
    CCR[0]    = temp[N];
    out[N-1:0]= temp[N-1:0];
    out[M-1:N]= 'b0;
  end
endmodule

Moved from comment: However this didn't compile. I have errors in line

CCR[0],out[N-1:0] and out[M-1:N]

# Error: VCP2858 adder.v : (16, 20): CCR[0] is not a valid left-hand side of a procedural assignment.
# Error: VCP2858 adder.v : (17, 28): out[N-1:0] is not a valid left-hand side of a procedural assignment.
# Error: VCP2858 adder.v : (18, 20): out[M-1:N] is not a valid left-hand side of a procedural assignment.

What is wrong with the above code?

Answer 1

Register data types are used as variables in procedural blocks. A register data type must be used when the signal is on the left-hand side of a procedural assignment. Since the default type of ports is wire you get an error. Changing your output ports to type reg should solve the problem.

output reg[M-1:0] out;
output reg[CCR_size-1:0] CCR;

Answer 2

Including the answer from @damage declaring the outputs as reg types, you also have CCR defined as 8 bits wide and then only assign the LSB.

The Bit growth from an Adder is 1 bit over the largest input.

I would implement as:

module adder(
  parameter N       =8,
  parameter CCR_size=8
)(
  input      [N-1:0]        inA,
  input      [N-1:0]        inB,
  output     [2*N-1:0]      out,
  output reg [CCR_size-1:0] CCR,
);
reg [n:0] sum;

always @* begin
  {CCR, sum}      = inA + inB;
end

assign out = sum; //Will Zero pad

endmodule